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How to import Eagle files to DxDesigner?

June 23, 2015, 12:30 pm
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Hello all,

 

I am trying to convert some Eagle files( .brd and .sch ) to DxDesigner? I want to modify these files in DxDesigner/Expedition 7.9.3

 

I have asked a similar question before on this forum but now I have PADS Standard Plus installed. I found on other forums that I can go from Eagle to Altium to DxDesigner but I can also use PADS.

 

I currently have installed Mentor Graphics Dx/Exp EE7.9.3 and I need to use this version for the Eagle files to make changes.

 

Is there a way to do this?

 

Thank you in advance.

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Generating layer stackup in drill drawing in PADS Layout

June 11, 2015, 12:30 am
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This script generates layer stackup  graphics in 2D library, which shall be imported in drill drawing through Drafting Toolbar > From library command

Thanks for Mentor team in writing the script.

 

graphical layer stackup.png

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Plane shape couldn't connect vias/pin

May 22, 2015, 12:14 am
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Hi All,

 

I am using EE2007.9.5 and I drawn a plane shape as usual but couldn't connect with corresponding through pin/vias.

 

I crosschecked both plane to pad ,other drc's and there are no any obstruct found that area.

 

Kindly refer below snapshot and suggest.

 

3

 

Thanks in advance.

 

Regards,

C.Senthil

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PADS Translator Tool

June 24, 2015, 10:53 am
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Hello,

 

Does anyone know if the PADS professional VX 1.1 come with a PADS Translator from Altium to Expedition?

 

I recently downloaded a 14-day license from PADS Professional Evaluation Download - Mentor Graphics .

 

I tried looking for the Altium translator under the Translators folder but I only see:

 

Allegro to PADS-Pro VX.1.1

DA to xDx Translator VX.1.1

DC to xDx Translator VX.1.1

DLib to xDx TranslatorVX.1.1

 

I am not sure if it was an installment issue~

 

Any help is appreciated.

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Altium to Expedition PCB 7.9.3 translator?

June 24, 2015, 12:11 pm
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Hello,

 

I am trying to import the layout of a file from Altium to Expedition PCB.

I am able to import the schematic from Altium to DxDesigner but I am trying to figure out if I can directly translate from Altium to Exp. PCB.

 

I am currently on the version Mentor Graphics Dx/Exp EE7.9.3.

 

I found a pdf (attached) that shows how to go from Altium to Dx/Expedition but you have to go through PADS. I currently have installed PADS Professional VX1.1.

 

I am not sure if the new PADS version will translate to the 7.9.3 Expedition since it is newer than Expedition.

 

Can I go around PADS or do I absolutely need it to get from Altium to Dx/Expedtion?

 

Any help is appreciated.

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LVS step Netlist vs Netlist

June 24, 2015, 6:34 am
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Hi all.

I am using Calibre LVS to compare two netlists.

I got a netlist by using S-edit, the second is derived from the GDS file.

But when I run the comparison, I get the error:

Source netlist references but does not define 2 subckts:

   nmos

   ptos

 

If I define nmos and pmos, I see in the report that the LVS see different instances.

 

This is a mistake netlist from S-edit or LVS is not working properly? How to fix it?

 

my netlist from S-edit: http://paste.fedoraproject.org/236140/14351523/

me netlist from LVS: http://paste.fedoraproject.org/236144/14351526

lvs report, when defined nmos & pmos: http://paste.fedoraproject.org/236145/15272314

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Enable floating license with USB dongle on a virtual Windows 8.1 machine within Windows Server

June 25, 2015, 1:12 am
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Hi,

 

I have installed the latest FlexNet on my machine , the dongle LED is red but the license log states "dongle not connected" :

 

dongle not connected: (p1=0, p2=0, p3=-10, p4=0)

8:24:18 (mgcld) retry Count = 3

8:24:20 (mgcld) dongle not connected: (p1=0, p2=0, p3=-10, p4=0)

8:24:20 (mgcld) retry Count = 2

8:24:21 (mgcld) dongle not connected: (p1=0, p2=0, p3=-10, p4=0)

8:24:21 (mgcld) retry Count = 1

 

The environment is a Windows 8.1 virtual machine on a Windows server. Since Hyper-V does not provide native USB support, a USB-to-LAN adapter is used to connect the dongle (via SX Virtual Link Software).

 

The dongle seems not visible for the virtual machine. Has anyone faced this problem? Any suggestions will be appreciated.

 

Best Regards,

Florin

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Hyperlynx IBIS model issue (DDR simulation)

June 3, 2015, 12:36 am
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Hi!

 

After I assign models and nets to simulate I receive the following error, while I try to perform the DDR3 batch simulation.

 

The following devices have inconsistent "Net to IBIS Model/Selector" mappings.

All signals of the same type should share the same IBIS Model/Selector.

Typically, this indicates that a signal net was not categorized correctly.

 

 

   Controller U10--

      Signal_Type  Pin#  IBIS_Signal  IBIS_Model/Selector  Net_Name

      DQS          M38   IP_DDR_0_DQSp BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_M38 CPU_DDR3_DQS0_P

      DQS          J38   IP_DDR_1_DQSp BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_J38 CPU_DDR3_DQS1_P

      DQS          F38   IP_DDR_2_DQSp BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_F38 CPU_DDR3_DQS2_P

      DQS          C38   IP_DDR_3_DQSp BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_C38 CPU_DDR3_DQS3_P

      DQS#         M37   IP_DDR_0_DQSn BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_M37 CPU_DDR3_DQS0_N

      DQS#         J37   IP_DDR_1_DQSn BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_J37 CPU_DDR3_DQS1_N

      DQS#         F37   IP_DDR_2_DQSn BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_F37 CPU_DDR3_DQS2_N

      DQS#         C37   IP_DDR_3_DQSn BCM28HPMFL3_T1XH_LPDDR3800M_CLK_DIFF_C37 CPU_DDR3_DQS3_N

      DQ           L36   IP_DDR_0_DQ0 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D0

      DQ           L38   IP_DDR_0_DQ1 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D1

      DQ           K33   IP_DDR_0_DQ2 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D2

      DQ           K31   IP_DDR_0_DQ3 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D3

      DQ           K34   IP_DDR_0_DQ4 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D4

      DQ           J34   IP_DDR_0_DQ5 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D5

      DQ           J31   IP_DDR_0_DQ6 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D6

      DQ           J32   IP_DDR_0_DQ7 GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D7

      DQ           G34   IP_DDR_1_DQ2 GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D10

      DQ           G33   IP_DDR_1_DQ3 GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D11

      DQ           H36   IP_DDR_1_DQ4 GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D12

      DQ           F31   IP_DDR_1_DQ5 GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D13

      DQ           G30   IP_DDR_1_DQ6 GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D14

      DQ           G31   IP_DDR_1_DQ7 GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D15

      DQ           F32   IP_DDR_2_DQ0 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D16

      DQ           E32   IP_DDR_2_DQ1 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D17

      DQ           F35   IP_DDR_2_DQ2 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D18

      DQ           E36   IP_DDR_2_DQ3 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D19

      DQ           E33   IP_DDR_2_DQ4 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D20

      DQ           E38   IP_DDR_2_DQ5 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D21

      DQ           D30   IP_DDR_2_DQ6 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D22

      DQ           D31   IP_DDR_2_DQ7 GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D23

      DQ           D34   IP_DDR_3_DQ0 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D24

      DQ           C35   IP_DDR_3_DQ1 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D25

      DQ           C34   IP_DDR_3_DQ2 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D26

      DQ           C32   IP_DDR_3_DQ3 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D27

      DQ           D33   IP_DDR_3_DQ4 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D28

      DQ           B35   IP_DDR_3_DQ5 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D29

      DQ           B38   IP_DDR_3_DQ6 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D30

      DQ           B33   IP_DDR_3_DQ7 GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_D31

      DM           J35   IP_DDR_0_DM  GRPIDQ0_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_DQM0

      DM           H33   IP_DDR_1_DM  GRPIDQ1_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_DQM1

      DM           F34   IP_DDR_2_DM  GRPIDQ2_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_DQM2

      DM           B36   IP_DDR_3_DM  GRPIDQ3_BCM28HPMFL3_T1XH_LPDDR3800M_SING CPU_DDR3_DQM3

 

What could be wrong here. Any help appreciated.

 

Regards,

M.

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is it possible to export and import the contraint in Pads Layout ??

June 25, 2015, 10:27 pm
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Hi,

how to export and import the contraint in pad layout.i am using same contraint for five board,(so instead fo entering the value ).is it possible to use the same contraint by using export and import option. or else is there any script file is available ??

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symbol editor

May 28, 2015, 4:27 am
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Xpedition Enterprise VX.1.1的symbol editor有两种吗？见下图，第一副图是别人的，和EE7.9的一样，能画出填充的多边形；第二幅是我的，界面和xDX Designer VX.1.1类似，能用直线画多边形，但无法填充多边形。另外，每次打开一个symbol，除了当前选项卡外，旁边还有一个选项卡不知道是干啥用的。

SR.jpgmy.JPG

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Change the default net name from xDX designer

June 25, 2015, 5:29 pm
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How can i change the default net name convention from $1234 to maybe norm$1234?

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How to integrate diodes into harness within Vesys harness design

June 26, 2015, 1:59 am
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Hello everyone,

 

I recently need to design a harness with diodes integrated. I read about other discussion related to resistor/diode integration posted previously. I understood that, I might need to create the diode as connector. However, I am not able to insert connector by putting node directly on the bundle(unlike splice). I am wondering how can I do that? I don't like to create a bundle node for this diode. The following example indicates what I would like to achieve.

 

 

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is it possible to hide the pin in PADS Logic ?

June 25, 2015, 9:37 pm
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Hi,

is it possible to hide the unused pin in pads logic ??i need to hide the pin 1 in U1 symbol.so how to hide it

padlogic.JPG

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How do I use the Valor NPI Sharelist "x,y" values to "pop" to that location in Expedition Layout ?

June 26, 2015, 6:09 am
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How do I use the Valor NPI Sharelist  "x,y" values to "pop" to that location in Expedition Layout  ?

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Pads Gerber,offset in Gerber tool(view mate ) ??

June 18, 2015, 2:30 am
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Hi,

i generated Gerber from Pads Layout 9.5.if i imported the Gerber in CAM Tool like View mate or CAM350.Gerber is not located in origin.Can any please reply for how to fix this issue.

even i set the Justification as Bottom left it is not located in origin point.

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Can I use Digi-Key's Designer Schematic as a front-end tool to Xpedition VX.1.1

June 26, 2015, 12:55 am
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Our customer wants to buy Digi-Key's Designer Schematic and Designer Layout by Mentor.

Is it possible to use the Designer Schematic as an front-end tool with Xpedition VX.1.1 as the back-end tool?

 

Designer Schematic

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Viewdraw 2004/2007 to 9.5 Migration

June 26, 2015, 7:26 am
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Comrades, I'm having difficulty converting old 2004 Viewdraw files to 9.5. The person that designed some of our older symbols had them set as Composite. The converter hangs up with the following:

00:00:05 Error: Default configuration for src2259c.1 cannot be created:

viewbase: Error 222: Error - Could not find WIR file FLTR_LORCH_1P75X0P500.1.

00:00:05 Migration stopped because schematics cannot be migrated to iCDB

 

I manually edit the symbol files with notepad, changing the Y 0 to Y 1 and change the data code to no avail. It still looks for the wire file. I tried changing the the W that was in front of the symbol in the .wir file to M:

 

W fltr_lorch_1p75x0p500 $14I76 ==> M fltr_lorch_1p75x0p500 $14I76

 

but that didn't solve it. There must be some other file this reference is in. Any help with this would be greatly appreciated.

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Where has my Connections Stream gone?

June 29, 2015, 12:17 am
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I have always followed a variety of topics using the Connection Stream. This used to be available by clicking on my name in the Community top-bar and from their I could navigate to my Connections Stream. It would show content from all the areas I follow in chronological order - very useful. However, today when I logged on, the menu under my 'name' looks different and I can't find my Connection Stream anywhere.

 

Has something changed? Can anyone tell me how to find that stream again?

 

UPDATE: It looks like this has been renamed from Activity to News. I found it by searching my history for a link to 'activity' which was re-directed to 'news'. So it can be found by typing "https://communities.mentor.com/news". However, I can't navigate here because I can't find 'News' on any menus.

 

Thanks,

Simon

 

Message was edited by: Simon Holdsworth

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Basic Script doesn't run with Excel 2013

June 29, 2015, 3:00 am
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I have some basic scripts for Pads Logic and Pads Layout who run with Excel 2010 but not with Excel 2013 ?

Anybody have a solution ?

Regards

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Defineing entry port names for Creo 2.0

June 28, 2015, 11:41 pm
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Hi!

 

I`m trying to make a 3D cabling diagram, from a VeSys wiring design, and I can`t find a way to define a connectors ENTRY_PORT property correctly. Normally, if I export a design to .nwf, the ENTRY_PORT property has a value "EP" (for all pins). I tried to make a property code named ENTRY_PORT, and add it to the connector pins (i was able to do this, but its really slow, and I would have to do it in every design again and again, but...) If I did this, in the .nwf file, the ENTRY_PORT values changed to the ones I defined, but another property with the same name, was added, with the same value. So it seems, VeSys defines the ENTRY_PORT property for the pins somewhere, but I can`t find, where, and how to edit the value of it. The same thing happens with the INTERNAL_LEN property, it has a default value, of "0" and if I add a property to each of the pins with the same name, it appears in the .nwf file duplicated, but in this case, the "original one" remains "0" and the second one has the value, I added. Please see the pictures below, for better understanding.

 

VeSys exports to .nwf normally like this:

 

normal nwf.PNG

 

It should be something like this (I manually overwrote the file, in this format it`s fully compatible with Creo):

 

shouldbe nwf.PNG

 

If I define ENTRY_PORT property for each pin:

 

PIN.PNG

 

definedentrryport.PNG

 

So, it would be great to store this ENTRY_PORT information, in the component library, so if I add a library part to a connector it automatically define the entry port names/values. But now, I simply cant find how to edit this parameter. Please help me with this problem!

 

Regards,

Lac

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