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Symbol Editor - difficulty selecting overlapping properties

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I'm editing/customizing a title block symbol. Some of the properties, such as @PRINTORDER and @SHEETTOTAL, are very close to each other horizontally. In this case, I want to see 'm of n' on the title block.

 

The name of the leftmost property, @PRINTORDER, is quite long so it overlaps with the @SHEETTOTAL property. The problem comes when I want to select one of the two overlapping properties such as @PRINTORDER, I can't do so - the @SHEETTOTAL property is selected. Even if I zoom in so that there space between the letters of @SHEETTOTAL and I directly click on one of the @PRINTORDER letters...the @SHEETTOTAL property is selected.

 

I was able to use the tcl window to select the @PRINTORDER property using the following sequence.

1. Click on the overlapped properties and @SHEETTOTAL is selected

2. Observe the object instance number of @SHEETTOTAL property in the tcl window

nse::selectitems 81

3. Select both @PRINTORDER and @SHEETTOTAL propertys by drag select. Note that the object instance number of @PRINTORDER is 81

nse::clearselection

nse::selectitems {75 81}

4. Select the @PRINTORDER property only using the following tcl command.

nse::clearselection

nse::selectitems 75

At this point the @PRINTORDER property is selected. Yeah!

But when I attempt to move this property, the selection changes to the @SHEETTOTAL property, so I can't now move the @PRINTORDER property

 

I've read through the symbol editor manual and looked through the settings. I can find no way to toggle through different items that are overlapping.

 

It would be nice if text selection worked like graphic selection. That is, if I click *inside* of a rectangle, the rectangle isn't selected. It is selected only if I click on one of the lines that makes up the rectangle. Text doesn't appear to work this way - clicking on white space between the letters causes text to be selected. In the case of overlapping text objects, which overlapping text object will be selected is not clear.

 

As a followup experiment I created two roughly equal length text objects. One text object had a number of spaces at the beginning while the other had a like number of spaces at the end. When I overlapped these text objects and clicked in the middle of the overlapped areas with the spaces, in both cases the same text object was selected. It appears that if the cursor is inside of a text bounding box then that text will be selected. Which text object is selected uses an unknown algorithm (lowest object ID?).

 

Hopefully I'm missing something and there's an easy solution. My workaround is to move whatever is selected (that I don't want to be selected) out of the way, position the now non-overlapping object at the desired location, then reposition the object that was moved. Any ugly hack at best...


ADMS error during spice simulation

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Hi,

I am doing a Serdes spice simulation using Hyperlynx 9.3. I am trying to incorporate a driver spice model as well as a connector touchstone model into the schematic. But, when both these models are incorporated, the tool gives an error saying, "Error: (eldo-1), unable to file models/SP-75594-0002_rev1.s16p". If I remove the connector model and use only the spice driver model in the schematics, the tool doesn't give any error and completes simulation.

 

I made sure that the said s-parameter file is inside the model library path. In fact the tool lets me assign models for the connector pins. Moreover, the tool doesn't give any error, if I replace the driver spice model with an ibis model and proceeds with simulation.

 

1. If I am using only spice model inside the schematic, the tool doesn't throw up any error.

2. If I am using ibis model and s-parameter model, the tool doesn't throw up any error.

3. If I am using both spice and s-parameter models inside the schematics, the tool gives the said error and simulation doesn't proceed.

 

I understand that ADMS is the simulator used for spice simulations. Can this be a licensing issue? or a simulation setting issue?

 

Regards,

Edward Anto A

Senior Research Engineer

C-DOT

Electronic City Phase-1

Bangalore.

Is there a decryption tool for EDX similar to the decryption for HKP's (data convert tool)?

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I'm interested in the ability to edit and extract portions of the total EDX content.

Can we use PartQuest Symbols in pads Logic?

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Hi Gray,

 

I am using both xdx designer and Pads logic (vx1.2) & I use part quest (Digikey) for downloading components in xdx,

So, is there any option to download part quest digikey Symbols/components in to PADS LOGIC, or can we import ".1" files in to PADS LOGIC.

Via modeling in hyper lynx IE3D solver.

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Hi,

I am simulating differential via having cases of back-drilling and without back-drill in order to observe impedance discontinuity. I selected the required 3D area and exported in 3D solver and observed return and insertion loss, while doing back-drill return loss should decrease return loss is increasing in my case while i am doing backdrilling. I think i am lagging in port assignments initially while exporting it asked for port for lower reference and upper reference, I assigned it as lower reference.

Can anyone help me in assignment of ports properly.

Thanks

3D via modelling in hyperlynx v9.2

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I am using hyperlynx v9.2 for 3D EM simulation, i have exported 3D area of differential via from board sim and assigned the ports, while simulating in MGRID it asks for meshing frequency i gave it as 6GHz and then simulated upto 6GHz. In simulation window it asked for number of points i gave it as 100. It simulated within 2 minutes which is very less time as compared to other softwares. When i imported s parameters in touchstone viewer return loss(S11)  and insertion loss (S21) graphs are not proper.I think it is not simulating all points.

Can you please help me where i am lagging.

No backups are made?

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Hi

Anyone seen that in some cases PADS does not generate backups - even if the design has changed several times during the day?

One of my colleagues has this problem. Sometimes the design is not backed up the entire day.

And - when PADS chrashes this has in some cases caused loss of an entire days work.

The backup schedule is set to every 5 minutes. Number of backups is 9.

It is not a harddisk space problem, he also made sure Crossprobing is turned off when not needing it. But still he experiences this problem from time to time.

It has been seen on more than one computer.

Any ideas?

 

regards

Klaus

Reusable blocks editor grayed out in CL

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We are using xDX Designer VX.0 pads flow.

The xDM library tools has the reusable blocks editor grayed out. Is this feature not available to use?

Also CL view in databook has a reuse blocks tab.

What is the best way for us to save a logical / physical reuse block using VX.0 pads flow?


library terminal overlap in symbol during symbol creation

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Does anybody know how to prevent a terminal been accidentally overlap with another terminal during library creation? Is there any script to verify library. The current Check part is not able to capture such error.

ECO Errors from PADS Logic to PADS Layout

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Hello All ,

 

We are facing ECO errors in generating correct data for placement files .

 

Sometimes even though the component is placed on the top and placement files is generated component gets swapped in placement file that is component layer comes out to be bottom and vice versa .

 

We use the ECO option ' Compare Names and Rename Nets and Parts as Necessary ' from PADS logic to PADS Layout before generating a placement file.

 

Swapping is found when

( 1 ) Component values are changed .

( 2 ) Some interfaces are directly removed from schematic .

 

But when we use the ECO option ' Compare Names but Prefer Add/Delete Parts to Renaming ' while facing this problem of swapping , parts do not get swap in placement file .Correct data is generating in the placement file with the above ECO option .

 

 

Why is it so ? Actually such errors should not be observed even if we choose ' Compare Names and Rename Nets and Parts as Necessary ' .

 

So please provide necessary guidance for the same .

 

How can we avoid such errors ?

looking for xDX - Project Close / Closing Event

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Hello,

I am looking for a Event which gets fired when I am closing the complete Project.

I found Events when

  • Closing a Schematic Sheet / Schematic Page
  • Closing / Shutting down xDX Designer

 

has someone here found something like this ?

Maybe it is undocumented, maybe I have overseen it. I tried all promising Events

listed in the Documentation, but none of them get fired when I close the whole Project.

 

I mean I can create a workaround, that when I like to query something from the

project, I check, if the object reference is still valid, but having an Event, would make my

whole project more simple with an event like Project Open / Close / Closing.

 

Thanks

 

Stefan

PASS THE REFDES VALUE FROM DXDATABOOK

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Hi, is it possbile to pass the REFDES value to a component in the schematic from the databook? I created different symbol for my RESISTORS table (resistor.1, jmp_resistor.1, etc,..) leaving the REFDES property value empty

 

In the databook i made a field named REFDES. Every component on the table have different REFDES value included "?" character (e.g: R?, JR?, etc..)

 

The PCB interface give me some error:

 

pcb: Note 6062: sym RESISTORS:JMP_RESISTOR: REFDES=: Changing property value to U?

 

pcb: Note 6062: sym RESISTORS:RESISTOR: REFDES=: Changing property value to U?

 

how can i edit the pcb config file to set custom refdes to the symbols?

How to get a list of open netlines

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How can I get list of open netlines in Expedition?

 

Thank you

Job not compatible with current version of program

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I've recently switched to a new laptop and re-installed PADS Layout, Logic, etc version 9.2.  I had 9.2 on my old laptop (both are Win7) and when I tried to open a file previously created and run on my old laptop, my new laptop gives me an error stating "Job not compatible with current version of program."  I have my hardware license key installed, but I can't even open or view the files now.

 

Any help/recommendations greatly appreciated.

 

Thank you.

Get Active Part Type in Pads Layout script

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I trying to get the substituted part from within a VB script in Pads Layout (the Active column)

 

If I list all parts in an assembly variant it possible to see if a specific part is substituted but how do I get the Part Type of the variant?

 

VB code for listing all parts of a part type in "asseblyvariant":

 

 

For Each part In ActiveDocument.AssemblyOptions(assemblyVariant).PartTypes(PartType).Components

      If part.Substituted Then

         kkkkkk =  AttrVal(part, "Value") ''' How do I point to the variant Part Type

     End if

Next part

 

 

 

                           

 

 

pads.bmp


Can´t start PCB Browser

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Hello,

 

I want to use the Mentor Expedition PCB Browser (xPCB Browser VX.1.1)

After installation I can´t start the Browser, and a windows failure occures:

 

 

Does anybody about this problem and can help me how can I start the PCB Browser?

 

Thanks in advance,

Kind Regards

Michael

Preventing License from being locked when network connection is lost

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We have a user who checks out a license for ModelSim. Everything works fine. However, when they lose internet connection and regain it back, the license is still locked. It will not recognize it being checked out even though the user has it. It is a network license which is on our server that becomes stale. We have to go through CMD to release the stale license and they are able to check it out again.

 

Is there a way to prevent this from happening?

HyperLynx signal- and power-integrity simulator has stopped working

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Hello All,

I'm using Hyperlynx 9.2 and recently I face an issue when selecting a signal, soon after selecting a signal HyperLynx stop working(not responding) and gets closed automatically. It also works fine with other board hyp files.

I get this error message only for some signals, whereas I'm able to select other control signals. The board is in work in progress.

will this error occurs if the net is not fully routed ?

I have attached the screenshot of the error message.

Could anyone please suggest, where I could have went wrong ?

Please let me know in need of more details about the issue.

 

Thanks in advance,

Regards,

Vineeth Sankarakutty

How to ignore the Power Net Extraction in an LVS BOX cell

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Hi ,

     I've a database with some IPs and clock tree network inside. The Power Supply for this one is distributed from TOP to each VDD/VSS Pin of std cells (used for clock tree network) and VDD/VSS Pin of IPs.

     Now, i want to extract parasitic data relating to clock tree network only (it will include : clock tree network cells + clock tree signal routing  + power distribution routing ), I've used LVS BOX to box all IPs. However, the parasitic data of Power Suppy Distribution (VDD/VSS) still contains the data of IP Power Routing.

     How can i get the parasitic data of Power Supply for Clock tree network only and ignore all the Power data belonging to IPs ?

 

Thanks,

Is it possible to export a Design Capture schematic to VisECAD?

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Is it possible to export a Design Capture schematic to a file-format supported by VisECAD? I have a .cce-file of my layout and would like to be able to crossprobe against the schematic.

 

Or do I have to convert the DC schematic to DxDesigner first, and then export it as a .cce-file?

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