i build 2 saperete symbols and connect them together with 1 PDB
but if i put them in dxd i get to RefDes
what can i do to force them to same RefDes
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how can build part with 2 identical gates -(nand)
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Upgrade to PADS Professional
Hi everybody,
I wonder why Mentor is talking about 3 PADS packages when PADS Professional is actually not PADS, but an Xpedition light version.
Suites are supposed to be “scalable”: PADS Standard/Plus and PADS Professional are not compatible, you just cannot work on the same layout with both tools. This is confirmed by the fact that Mentor is actually not allowing any upgrade to PADS Professional. You have to pay a new licence.
I bought a PADS licence last year. I spent a lot of time time building libraries for netlist project, and then PADS moved to the Integrated Flow a few months later… Let’s loose some more time on building the Central librairies.
Integration of DxDesigner, Layout, Router and Central Libraries is really poor, and so far, I have never met any software with so many bugs. I can not even count how many times I sent my project to maintenance because of weird things happening.
Given the endless list of problems I've been face to using PADS, and the poor productivity achieved, I could think Mentor is just pushing people to move to Xpedition technology (=PADS Professional), and leave PADS dying.
I am having a really bad experience with PADS, and I would expect Mentor to allow me to upgrade my package to PADS Professionnal. But they do not want to. I am not going to buy a new PADS Professional licence, even with some discount. What am I supposed to do with my current license? A huge amount of money thrown away.
I know a load of PADS users feel the same. And are just moving to Altium. Should I do the same?
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DxDesigner Source Schematic Files
I recently moved companies and my new employer just upgraded to Xpedition.
In previous DxDesinger versions the schematic source files were stored in ./SCH/, much like the symbol files that are still stored in ./SYM/. The visibility made it very easy to write scripts and use automation to reduce design time.
As so far as I can tell these files have been moved to some sort of database structure. Is there any way to still manipulate the source schematic files while not having to use the GUI?
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How to show total number pins in connector in Vesys 2.0 schematic
Helo,
As am working in schematic style set alteration I want to show total number pins in a connector. And it should called from vesys component library. I have tried this option to show number of pins in a connector, but I got only the option "number of pins in use". If anybody having idea how to show the total number of pins in a connector, let me know.
Thanks and Regards,
Manoj
+91 8973234943
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Tessent Shell: Path detail for transition fault report
Hello,
my question is about Tessent shell, after performing a pattern simulation for transition faults.
Is it possible to know the paths that a transition fault is tested through during pattern simulation?
I can see when generating a fault report, for each fault, the delay information is shown for both the longest true path through the fault and the tested path.
so I was wondering if it is possible to know the exact paths for which these delay numbers are reported.
Thank you,
Omar
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DFT Audit when upgrading to PADS Standard Plus
My VAR is telling me that my current DFT Audit license it will not work if I upgrade to PADS Standard Plus. It is ONLY almost 3 grand to maintain this functionality with the purchase of the
PADS Standard Plus Packaging .
Is this true? I did a small test and it still seams to be working. What is he referring to?
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How to start the PCB DESIGN (after finished schematic in DxDesigner) with Expedition PCB? // I get ERROR "Can't import layout template."
Hello,
I want to start the PCB design (I use Expedition Enterprise 7.9.5) and therefore click on the tool "Expedition PCB"(in DxDesigner). The "DxDesigner to Expedition PCB" window opens.
I have to choose:
a) central library (is already chosen and shown greyed / locked)
b) select template
c) PCB directory (already chosen, but I can make changes)
After selecting my template and PCB directory I click OK and I get the following error: "Can't import layout template."
What could be the problem?
Which rules do I have to follow, to make sure the template can be imported?
What are the interactions between Central Library, Template and PCB Directory? Can there be incompatibilities between them? Makes ist a difference, where the Central Library is located and where the Template is located?
I designed my own template in the folder " 7.9.5EE \ SDD_HOME \ standard \ templates \ PCB \ Central Library \ templates \ layout \ 4 Layer Template \" . I did it using the "layout template editor" in the "Library Manager". I copied a 4 layer template and edited the template in Expedition PCB and saved it. Before the PCB window, there comes a selection window where I can choose Pinnacle, Ascent LX or Ascent. I chose Pinnacle. But what do these options mean?
Maybe I have to do something to make the template accessable for the "Expedition PCB" ? What are the standard rules for this to note?
It would be nice, if you could describe me, if this is the right way to make a template, or I did something wrong.
Maybe I should use following method to create new PCB design? :
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Invoking Expedition PCB
Use the following steps to invoke Expedition PCB software and create a new PCBdesign file:
- Select Start > Programs > Mentor Graphics SDD > Layout > Expedition PCBto invoke Expedition PCB software (if not already invoked). The Expedition PCB window appears.
- Click File > New; the Job Management Wizard appears.
- Click the Browse icon on the Job Management Wizard and browse for the following source project filename:
- Click Next; the software creates a new PCB source project filename (gate_test.pcb).
- Select 4 Layer Template in the Job Management Wizard and click Next to advance to the next dialog box.
- Click Finish to accept the default settings.
- Click Close to exit the Job Management Wizard dialog box.
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Thank you in advance.
Nachricht geändert durch Andreas Lechner
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how to auto select splice and heat shrink sleeves PN?
Hi
i need to auto select splice and heat shrink sleeves in Capital HarnessXC .
but it's always not sucessful.
i try it according to the user guide, but it's not very clear in the user guide.
1、Are there some docment to introduce what i should take care in Capital Library?
2、 i don't need assign PN to splice in Capital Harness, if i can auto select HSS for Splice in Capital HarnessXC ?
Thanks and Best Regards.
Louis
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in VX1.1 howcan i place components directfrom dxd to pcb in cross prob
after annotating the design i start
placing but i didnt maneged to place direct from the dxd
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how to back-annotate bundle length from Capital HarnessXC to Capital Integrator?
Hi
I sychronize Harness bundle from Capital Integrator to Capital HarnessXC .
and i change some bundle length in Capital HarnessXC.
Can i back-annotate the changed bundle length to Capital Integrator?
Thanks and best regards.
Louis
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Jiffy Splice
Hello,
What is the best way to deal with jiffy splices? They are a connected male and female terminals covered by a sleeve. As a connector I always have to create a zero length bundle to show both wires coming in from either side. As a splice the terminals could be additional components but you can't assign the male/female terminal to its designated wire. This would probably create an issue down the line when running it through TVM as the terminals get terminated like any other wire.
Any ideas?
Thanks!
Lorena
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Pyxis_SPT license problems
Hello,
I've been administrating a Mentor Graphics class for a short period, unfortunately I'm not the one who installed and configured everything in the beginning, so I might be incompetent in some aspects. The problem is quite strange: we have a server machine with the installed license and 15 client computers running Windows (for Expedition PCB and other) and Linux RedHat Enterprise 5.7 (Pyxis_SPT and Calibre). Expedition PCB and all the other windows products are working on all the computers including the server, no license problems occur. When we switch to Linux, Pyxis_SPT works only on 13 of the 15 client computers. All the computers are linked to one network via a switch, are in the same IP range and etc. On the two computers Pyxis Project Navigator opens, but when Pyxis Schematic (or Layout) is invoked it crashes right away. The log file from Pyxis:
// Pyxis Schematic v10.1_0.0 Mon Jan 23 08:51:39 PST 2012
//
// Copyright Mentor Graphics Corporation 1982
//
// All Rights Reserved.
//
// THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
// WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR
// ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
//
// Mentor Graphics software executing under x86_64 Linux.
//
$change_workspace("Tabbed");
// Note: Default ripper symbol pathname for auto-ripper instantiation set to $MGC_IC_GENERIC_LIB/rip/1X1 (from: Capture/gdc/note 98)
// Note: Activated Variant hotkeys. (from: Uims/base_toolkit/ui_session_tk 81)
// Note: Reading version 1 of sheet $PYXIS_SPT/GenericPLL/TopDown_Assembly/4_bit_counter/schematic/sheet1 (from: Capture/gdc/note 82)
$set_active_window("Schematic#1");
// Note: Executing $GENERIC13/userware/da_ic/schematic.dofile (from: Capture/gdc/note 99)
// Fail:
// License request for icarch feature failed (from: Core/licensing/MGLS_run 03)
// License request for Pyxis Schematic failed.
All the environment variables are set and do not differ from the ones set on the working computers. The license seems to be working and it is available on all the computers. Here is the mgls_ok command output on the computer where Pyxis isn't working (license is granted for icarch and pyxschematic_c):
$ mgls_ok -pd 1997.07 icarch
Checking availability of "icarch".
License granted through "pyxschematic_c".
And here is part of the lmstat -a command output:
lmstat - Copyright (c) 1989-2008 Acresso Software Inc. All Rights Reserved.
Flexible License Manager status on Fri 12/11/2015 14:55
License server status: 1717@mentor-server
License file(s) on mentor-server: C:\MentorGraphics\lic\license.dat:
mentor-server: license server UP (MASTER) v11.10
Vendor daemon status (on mentor-server):
mgcld: UP v11.10
Feature usage info:
Users of acctree: (Total of 30 licenses issued; Total of 0 licenses in use)
Almost forgot to mention: the MGLS_DEBUG_LOG is the same for the working and non-working computers.
If anyone has any suggestions or advice, please comment. I can send any other logs or info if needed.
P.S. I know we are using outdated license software, but we would like to keep it that way for now (if possible).
P.S. Also sorry for my English.
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Have Mentor fixed a bug in Export to ODB++ command?
Hello All,
When exporting ExpeditionPCB design to ODB++, in the ODB++ Output dialog there are options for Non-functional pad removal related to Pins (None or Unused Pins) and Vias (None or Unused Vias). These options work fine for a layer defined as a signal layer, but work badly for a layer defined as a plane layer. I mean that for a plane layer Mentor doesn't remove unused pins and vias, even if the above options are set to Unused Pins and Unused Vias.
That was for ExpeditionPCB 7.9.5. Does anybody know if this bug is fixed in the latest version?
Oleg
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error: Can not open DxDesigner project doing the forward annotation
Hello to All,
When I try to make a forward annotation from DxDesigner to PADS Layout (DxDesigner is closed) it shows me an error: Can not open DxDesigner project.
If I have my schematic opened manually it connects, but when I press "Forward to PCB" it shows the following info:
pcb: Note 5996: Using Config File C:\MentorGraphics\9.5PADS\SDD_HOME\standard\pads95.cfg
pcb: Warning 5720: Check PSDB.err for VIEWBASE messages
pcb: Error 5709: Could not open schematic PSDB
pcb: Note 5626: Summary of Log Files/pcb.err
Status 0, Notes 1, Warnings 1
Errors 1, Failures 0, Fatals 0, Internals 0
viewbase: Error 222: Error - Could not find WIR file PSDB.1.
(PSDB it is name of the Project)
I cannot understand what is the problem and how to solve it.
Can somebody help me please?
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DxDatabook problems // Library problems
Hello,
in the DxDatabook I have a lot of problems in the verfication of components window (zero matches, multiple matches, cannot find library).
I use the HLA Library template and didn't change the "Location" and "Central Library" paths. Is this a potential problem? Should I change the path? Can I change the path now without problems in my project (I did schematic already)?
1.) All my own parts have "?" ("cannot find library") marker in DxDatabook verification window. I designed them in the parts editor -> new parts -> enter part number of the part. If double click in verification window -> errormessage: "The loaded symbol bjt:BCR is not included in the list of valid symbols for this component. The component has been loaded, but the symbos previewer has not been set." Any idea what this means?
2.) All copied parts which i copied in the part editor are red marked (zero matches).
(I copied them from existing parts in the CENTRAL LIBRARY in library manager (named HLA_CentralLibrary))
3.) If I use the original existing parts directly from HLA_CentralLibrary (this is the only library in my library editor window, should there be more?), then there is only a yellow marker (multiple matches).
Something must be wrong with my library usage? Or are there some wrong settings in my library template? I use the HLA_Library template and didn't change the "Location" and "Central Library" paths.
Thank you in advance.
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Three different symbols(different number of pins) (in DxDesigner schematic) for the same part.
Hello,
I need a part with three different symbols to place in the schematic. The total amount ofpins of the part distribute to the three differentsymbols( symbol A 8 pins, symbol B 3 pins, symbol C 3 pins). How is it possible to do that? How does the pinmapping work with multiple symbols? Do the symbols need the same REF DESIGNATOR or NAME or LABEL?
Is there an other possibility, maybe place the remaining pins in the schematic solo?
I must do this dividing in different symbols in order to make the drawing of the schematic easier and clearly arranged.
Thank you very much.
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VX1.2 Download
In the "5 Ways to Maximize the Benefits of 3D Layout Webinar" Jim said it is NOW available for download from support net. I can't find it. Where is it located?
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Using Constraints to Make PCB Layout Easier
Hey all,
Just wanted to bring to your attention that Mentor's Vern Wnek has recently written an informative article for Printed Circuit Design & Fab on the pros and cons of using constraints. The article, titled "Using Constraints to Make PCB Layout Easier," also provides a step-by-step procedure for effective constraint entry.
Check it out, and let us know what you think!
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How to define clearance for a net or a part
I need to define 7mil trace to pad clearance for all pads on a connector. The master is 10mil and it says it is read only from Expedition.
I see that there is no place to give a net or part clearance rules. Please help.
The CES is very confusing.
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DESIGNrev scripts to share
Hi DESIGNrev users,
My colleague Saunder has been looking into several ideas for Tcl scripts that run in DESIGNrev. We’re wondering if any of the following topics would be of interest to folks here in the Calibre Communities. If you see something you think would be useful for you or someone else would you let us know by posting a response to this thread? If any of these generate interest then we will finish them up and share them with the community.
NOTE: another use for scripts like these are to use as a base to make changes to, and accomplish something slightly different you may be interested in. These kinds of scripts can be very easy to modify and also very easy to use in DESIGNrev.
- 1. Get the total area of selected polygons.
- 2. Save the current DESIGNrev window view in a png format.
- 3. Create overlay and open RVE to view the XOR results in one step
- 4. Compare 2 DRC sets of results.
- 5. Get database’s information without opening the design ( such as, cellnames, Topcells, precisions…etc)
- 6. Rename a list of cells to avoid conflict on cellnames
- 7. Change the database format from GDS to OASIS file
- 8. Create your own DESIGNrev Macro’s menu
Reply to this post to let us know which of these capabilities would be valuable to have and we’ll work on making those scripts available first.
Best regards,
Chris & Saunder
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