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Ability to export all Part data from VeSys Components

May 29, 2008, 2:10 pm
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A limited amount of data can be exported from VeSys Components (in the ACES format), it would be useful to be able to access other data that VeSys Components particularly if you want to create some custom reports or interface with other company databases - this output format could be xml or a delimted text file.

It would also be useful if VeSys Components could import more data, new customers often have some legacy data that needs to be imported into VeSys Components but this is limited by the ACES format.

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Calibre Model-based Planarity Flow for TSMC’s 65 and 40 nanometer IC Manufacturing Processes

May 29, 2008, 10:31 am
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Mentor Graphics Corporation (Nasdaq: MENT) today announced that its SmartFill model-based planarity flow has been qualified for TSMC's 65 and 40 nanometer (nm) processes. By reducing metal thickness variability, model based metal filling can help improve systematic and parametric yield. The SmartFill flow integrates the Calibre® CMPAnalyzer and YieldEnhancer facilities, and TSMC's DFM (design for manufacturing) data kit (DDK). The SmartFill qualification is a continuation of the DFM between Mentor Graphics and TSMC under TSMC's Active Accuracy Assurance (AAA) program.

 

"Making the best use of foundry data in an accurate and consistent manner with EDA partners is a goal of our AAA initiative. We envision further collaboration with Mentor Graphics as AAA expands to capture more of advanced process technologies' inherent value," said S.T. Juang, Sr. Director of Design Infrastructure Marketing, TSMC.

 

 

The Calibre CMPAnalyzer tool is the foundation of the Mentor CMP solution. CMPAnalyzer is directly linked with VCMP, TSMC's CMP simulator, to provide 3-D hotspot detection and to determine an optimum filling strategy. CMPAnalyzer then passes the appropriate information to the SmartFill function of the Calibre YieldEnhancer tool, which adds the fill elements directly into the layout design database. The combination of accurate foundry data and intelligent fill analysis improves parametric yield by reducing thickness variation that affects resistance while minimizing the capacitance added to the design. CMPAnalyzer also generates thickness values that can be incorporated into the Calibre xRCTM tool for more accurate parasitic extraction. CMPAnalyzer and YieldEnhancer are built on the Calibre nm Platform, the industry's leading physical verification platform known for delivering best-in-class performance, accuracy, and reliability.

 

 

 

 

 

To see more of the press release, go to:

 

 

http://www.mentor.com/company/news/calibremodelbasedplanarityflowtsmcs6540nanometericmanufacturingprocesses.cfm

 

 

 

 

 

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Floating License Server / Dongle Drivers / Installation Guide

May 21, 2008, 1:03 am
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The Floating License Server / Dongle Drivers / Installation Guide used to be available for download from the www.vesys.com/techsupport website, this website now redirects to a Mentor graphics sales page does anyone know where these can be downloaded or if they are available?

 

 

I am guessing that the 2007.2 software download may contain these files but I don't want to download a 45Mb file just for these files, having to download the full release (which is now out of date because 2007.2.2 is available) seems a bit strange and a bit of a chicken and egg situationin in order to get the installation guide!!!!

 

 

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Can I setup my Laptop to work Locally & on a Network

May 16, 2008, 2:55 pm
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I have a laptop and want to work both on a network and locally on the C: drive.  I work in the office and occassionally from home, has anyone created a configuration that will enable a local and network setup?

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Mentor bolsters Calibre DFM toolset with Ponte acquisition

May 15, 2008, 3:26 pm
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In order to help reduce the impact of process variability during semiconductor design and manufacturing, Mentor  has acquired the assets of Mountain View, Calif.-based Ponte Solutions Inc, a developer of model-based design for manufacturing (DFM) software tools.

 

With the acquisition of Ponte,Mentor expands its efforts in the design-for-manufacturing (DFM) arena. Ponte's solutions analyze, predict, and reduce the impact of process variability during the manufacture and design of semiconductors.

 

Here's the link to the article on EDN:

 

http://www.edn.com/article/CA6561308.html

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modelling inrush current on HID lamps

April 23, 2008, 3:17 am
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High Intensity Discharge lighting is becoming more common in lighting.  Normal operating current consumption is significantly lower than incandescent bulbs of similar light output, but  startup current can be very large – several times the normal operating current, and the wiring must be designed to accommodate this.

 

 

 

 

 

Here’s the way to model this in VeSys:

 

  • Create a custom component, as shown, and set the inrush path’s load to the specified inrush current.

  • Build the design, as normal

  • Define Named Switch States for both the startup condition – inrush switches closed - and the normal operating conditions.

  • Test the wiring using the startup state

 

 

 

 

 

 

 

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using layers with simulation

April 23, 2008, 3:51 am
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Some designers need to create complex custom components with custom graphics shown on the drawing, but they still want to operate the internal switches and relays for simulation - layers can help . . .

 

  • Create a layer called "internals", or whatever

  • Create your custom component with all the necessary internal components and wiring - switches, relays, loads, logic links, pcb links and so on.

  • Assign each of the internal items to the "internals" layer

  • Switch off the Outline box and create the graphics needed for the printed drawing

  • Purge and save it as a block

  • Repeat this process for the other custom components.

 

When you use these custom components in a wiring design you will now be able to toggle the display of the internal components in every custom component by simply toggling the "internals" layer in the Layers popup

 

 

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Hydraulics

April 23, 2008, 3:18 am
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Has anyone tried using VeSys for hydraulics design.  It looks like it can be done, but are there any tricks I need to know ?

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Is there a free viewer ?

April 23, 2008, 3:56 am
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Is there a free viewer to view VeSys designs ?

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Is it acceptable to have a wire part number which ends with an "_"

May 15, 2008, 7:24 am
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I have wires part numbers that end with "_" and for some reason the part numbers are not being selected in Harness.  Has anyone had any experience of this

 

 

Paul

 

 

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Calibre xRC/xL Error: Net Information could not be built. Error: The inputs for the inductance engine could not be properly built

May 15, 2008, 11:17 am
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Here's some information from a tech note in Supportnet that was recently published: MG242346

 

 

Symptom:

 

 

When performing an inductance extraction if you encounter these errors below:

Error: Net Information could not be built

 

Error: The inputs for the inductance engine could not be properly built

 

 

Causes:

 

 

The Errors cited could be caused by a missing return path.

 

Look for a missing return path warning in your log file.

 

The warning notice appears as follows:

 

     Warning: "No Return paths could be found" for inductance extraction.

 

 

Solution:

 

 

If there are any nets that are specified as the nets to be used as return paths for inductance extraction, make sure that you include proper texting for all such nets in the layout file as well.

 

For example:

 

If you specify POWER and GROUND nets as the nets to be used as return paths in your SVRF rule file using these statements:

 

                        PEX POWER LAYOUT vdd!

                        PEX GROUND LAYOUT vss!

 

Make sure you have these exact same named POWER and GROUND nets in your layout file.

 

The lack of a defined return path will result in the above mentioned Warning and Errors.   

 

 

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Mentor Graphics Aligns Product Groups to Address IC Implementation Challenges at 45nm and Beyond

May 15, 2008, 11:11 am
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Mentor Graphics Corporation (NASDAQ: MENT) today announced it has aligned its integrated circuit (IC) implementation product lines under the Design-to-Silicon division to better address the design and manufacturing challenges of 45nm and smaller process nodes. The division, which will be headed by vice president and general manager, Joseph Sawicki, will now include Mentor's industry-leading IC products: the Olympus-SoCTM place-and-route system, the Calibre® physical verification and DFM platform, and the design-for-test (DFT) product line.

 

 

http://www.mentor.com/company/news/icimplementationchallenges45nm.cfm

 

 

 

 

 

 

 

 

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Reports in CSV or Tab delimited formats

May 15, 2008, 9:52 am
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I'd like to see the files generated by Harness Reports to be in a delimited text file format which contains all of the data.  At the moment it only seems possible to export all of the data fields in the HTML format, which is OK view but not very useful if you want to import it into your own PDM or data management system.  To interface with other systems we have had to write our tools to read the html files and convert them into a more useable format, this is not very practical to do and is quite time consuming as the html format is not very easy to read.

 

 

 

 

 

Anyone got any better ideas on how this could be done?

 

 

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Auto populate a VeSys Components database

April 23, 2008, 3:58 am
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Is it possible to auto populate a VeSys Components database

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Support documents for the Calibre xRC CalibreView Integration into the Cadence Virtuoso Design Environment

May 5, 2008, 2:40 pm
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There's a new tech note inside the Mentor Graphics SupportNet site that talks about the available support documents for the Calibre xRC calibreview integration into the Cadence Virtuoso environment. The technote ID is MG56823, and it describes the application notes and documentation that is related to creation of cell mapping files, extraction and simulation with Calibre Interactive and Virtuoso and ADE, and creating graphical extracted views.

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System to Improve RET-OPC Production by Dynamic Design Coverage Using Sign-off Litho Simulator

May 5, 2008, 2:26 pm
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There's a new paper that came out at SPIE called System to Improve RET-OPC Production by Dynamic Design Coverage Using Sign-off Litho Simulator. It's an article that talks aboiut allowing RET/OPC production systems to reach maturity faster through detailed collection of hotspots identified at the design stage. The advanced process technologies have well known yield loss due to the degradation of pattern fidelity, and this paper addresses this issue.

 

 

http://spiedl.aip.org/getabs/servlet/GetabsServlet?prog=normal&id=PSISDG00692500000169250X000001&idtype=cvips&gifs=yes

 

 

It's written by Mark Simmons, Jean-Marie Brunet , and YK Kim (Mentor Graphics), and Seung-Weon Paek (Samsung).

 

 

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Automatically Displaying Calibre pull down menu on Cadence Schematic viewer

April 30, 2008, 4:04 pm
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The Calibre pull down menu does not show up automatically on the Cadence Schematic Viewer.

I need to click on Analog Environment first, for the Calibre menu to show up.

I am using 2007.3 version of Calibre and 5.1 version of Cadence Virtuoso.

 

How can I have the Calibre menu displayed automatically??

 

 

 

 

 

 

 

 

Thanks

 

 

Architha

 

 

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UMC validation of nmDRC for 65 nm

April 30, 2008, 3:05 pm
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Did Mentor Fix the "Remove unused pads" for High-Speed Signals?

July 25, 2016, 9:10 am
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When routing high-speed signals via pads in the board stack-up create parasitic capacitance. Much of the literature recommends removing unused pads except where necessary for routing.

 

I thought I remembered removing unused pads through the "options", but then having copper (plane or pour) flood based on the copper-to-drill rule. This then caused via pads on some layers to create capacitive coupling that was worse than leaving the pads in play.

 

Further, there were issues where the accuracy (or inaccuracy) of the drill would be fine if the pad was there. Basically the drill hole placement could "float" within the bounds of the via pad, but that was okay. What was NOT okay was if you removed via pads, then the copper-to-drill would allow the copper to flood closer to the drill such that sometime the drill would go through the copper plane and short out (or at least the "good" board house flagged this as a violation).

 

I see the "help" on the "Remove unused pads" option says the tool replaces unused pads with anti-pads. Is this how Mentor fixed this issue sometime between PADS 9.5 and PADS VX.1.2?

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Routing differential pairs traces

November 3, 2009, 1:56 am
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I need to route some differential pair traces, using a width of 12.5 thou seperated by 8 thou.

 

I have set the width and spacing in the "Differential Pair" settings in the "Design Rules" for the pair of nets.

 

How do you then go about routing these traces, can it only be done using PADS Router ?

 

I dont want to route them using PADS Router.

 

I would like to manually route the differential pair of traces, but I want the trace width and spacing to be done automatically.

 

Is there any way of doing this ?

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